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嵌入式培訓(xùn)

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研發(fā)與生產(chǎn) 脫產(chǎn)就業(yè)培訓(xùn)基地
3G通信 企業(yè)培訓(xùn) 
  首 頁   手機(jī)閱讀   課程介紹   培訓(xùn)報(bào)名  企業(yè)培訓(xùn)   付款方式   講師介紹   學(xué)員評(píng)價(jià)   關(guān)于我們   聯(lián)系我們  承接項(xiàng)目 開發(fā)板  網(wǎng)校
嵌入式協(xié)處理器--FPGA
FPGA項(xiàng)目實(shí)戰(zhàn)系列課程----
嵌入式OS--4G手機(jī)操作系統(tǒng)
嵌入式協(xié)處理器--DSP
手機(jī)/網(wǎng)絡(luò)/動(dòng)漫游戲開發(fā)
嵌入式OS-Linux
嵌入式CPU--ARM
嵌入式OS--WinCE
單片機(jī)培訓(xùn)
嵌入式硬件設(shè)計(jì)
Altium Designer Layout高速硬件設(shè)計(jì)
嵌入式OS--VxWorks
PowerPC嵌入式系統(tǒng)/編譯器優(yōu)化
PLC編程/變頻器/數(shù)控/人機(jī)界面 
開發(fā)語言/數(shù)據(jù)庫/軟硬件測試
3G手機(jī)軟件測試、硬件測試
芯片設(shè)計(jì)/大規(guī)模集成電路VLSI
云計(jì)算、物聯(lián)網(wǎng)
開源操作系統(tǒng)Tiny OS開發(fā)
小型機(jī)系統(tǒng)管理
其他類
 
      Synopsys Prime Time 1 培訓(xùn)班
   入學(xué)要求

        學(xué)員學(xué)習(xí)本課程應(yīng)具備下列基礎(chǔ)知識(shí):
        ◆ 電路系統(tǒng)的基本概念。

   班級(jí)規(guī)模及環(huán)境--熱線:4008699035 手機(jī):15921673576/13918613812( 微信同號(hào))
       堅(jiān)持小班授課,為保證培訓(xùn)效果,增加互動(dòng)環(huán)節(jié),每期人數(shù)限3到5人。
   上課時(shí)間和地點(diǎn)
上課地點(diǎn):【上�!浚和瑵�(jì)大學(xué)(滬西)/新城金郡商務(wù)樓(11號(hào)線白銀路站) 【深圳分部】:電影大廈(地鐵一號(hào)線大劇院站)/深圳大學(xué)成教院 【北京分部】:北京中山/福鑫大樓 【南京分部】:金港大廈(和燕路) 【武漢分部】:佳源大廈(高新二路) 【成都分部】:領(lǐng)館區(qū)1號(hào)(中和大道) 【沈陽分部】:沈陽理工大學(xué)/六宅臻品 【鄭州分部】:鄭州大學(xué)/錦華大廈 【石家莊分部】:河北科技大學(xué)/瑞景大廈 【廣州分部】:廣糧大廈 【西安分部】:協(xié)同大廈
近開課時(shí)間(周末班/連續(xù)班/晚班)
Synopsys Prime Time 1 培訓(xùn)班:2024年11月18日.....(請(qǐng)抓緊報(bào)名)
   實(shí)驗(yàn)設(shè)備
     ☆資深工程師授課

        
        ☆注重質(zhì)量
        ☆邊講邊練

        ☆合格學(xué)員免費(fèi)推薦工作

        

        專注高端培訓(xùn)17年,曙海提供的課程得到本行業(yè)的廣泛認(rèn)可,學(xué)員的能力
        得到大家的認(rèn)同,受到用人單位的廣泛贊譽(yù)。

        ★實(shí)驗(yàn)設(shè)備請(qǐng)點(diǎn)擊這兒查看★
   新優(yōu)惠
       ◆在讀學(xué)生憑學(xué)生證,可優(yōu)惠500元。
   質(zhì)量保障

        1、培訓(xùn)過程中,如有部分內(nèi)容理解不透或消化不好,可免費(fèi)在以后培訓(xùn)班中重聽;
        2、培訓(xùn)結(jié)束后免費(fèi)提供半年的技術(shù)支持,充分保證培訓(xùn)后出效果;
        3、培訓(xùn)合格學(xué)員可享受免費(fèi)推薦就業(yè)機(jī)會(huì)。

        Synopsys Prime Time 1 培訓(xùn)班
本課程可幫助IC工程師進(jìn)一步全面系統(tǒng)地理解IC設(shè)計(jì)概念與方法。培訓(xùn)將采用Synopsys公司相關(guān)領(lǐng)域的培訓(xùn)教材,培訓(xùn)方式以講課和實(shí)驗(yàn)穿插進(jìn)行。
Overview
This workshop shows you how to maximize your productivity when using PrimeTime. You will validate and enhance run scripts, quickly identify and debug your design violations by generating and interpreting timing reports, remove pessimism with path-based analysis, and generate ECO fixing guidance to downstream tools.
Topics include:
  • Preparing for STA on your design, including investigating and analyzing the clocks that dictate STA results
  • Validating inherited PrimeTime run scripts
  • Leveraging the latest PrimeTime best practices to create new run scripts
  • Identifying opportunities to improve run time
  • Performing static timing analysis
  • Providing ECO fixing guidance to downstream tools
Objectives
At the end of this workshop the student should be able to:
  • Interpret the essential details in a timing report for setup and hold, recovery and removal, and clock-gating setup and hold
  • Generate timing reports for specific paths and with specific details
  • Generate summary reports of the design violations organized by clock, slack, or by timing check
  • Validate, confirm, debug, enhance, and execute a PrimeTime run script
  • Create a PrimeTime run script based on seed scripts from the RMgen utility
  • Identify opportunities to improve run time
  • Create a saved session and subsequently restore the saved session
  • Identify the clocks, where they are defined, and which ones interact on an unfamiliar design
  • Reduce pessimism using path-based analysis
  • Use both a broad automatic flow for fixing setup and hold violations and a manual flow for tackling individual problem paths.
Audience Profile
Design or verification engineers who perform STA using PrimeTime.
Prerequisites
To benefit the most from the material presented in this workshop, students should have:
  • A basic understanding of digital IC design
  • Familiarity with UNIX workstations running X-windows
  • Familiarity with vi, emacs, or other UNIX text editors
Course Outline
階段一
  • Does your design meet timing?
  • Objects, Attributes, Collections
  • Constraints in a timing report
  • Timing arcs in a timing report
  • Control which paths are reported
階段二
  • Summary Reports
  • Create a setup file and run script
  • Getting to know your clocks
  • Analysis types and back annotation
階段三
  • Additional checks and constraints
  • Path-Based Analysis and ECO Flow
  • Emerging Technologies and Conclusion
 
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.(2024年11月18日.....(請(qǐng)抓緊報(bào)名))....................................
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