 PrimeRail培訓(xùn) |
| 培養(yǎng)對象 |
1.理工科背景，有志于數(shù)字集成電路設(shè)計(jì)工作的學(xué)生和轉(zhuǎn)行人員；
2.需要充電，提升技術(shù)水平和熟悉設(shè)計(jì)流程的在職人員；
3.集成電路設(shè)計(jì)企業(yè)的員工內(nèi)訓(xùn)。
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| 入學(xué)要求 |
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學(xué)員學(xué)習(xí)本課程應(yīng)具備下列基礎(chǔ)知識：
◆電路系統(tǒng)的基本概念。 |
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班級規(guī)模及環(huán)境--熱線:4008699035 手機(jī):15921673576/13918613812( 微信同號) |
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堅(jiān)持小班授課，為保證培訓(xùn)效果，增加互動環(huán)節(jié)，每期人數(shù)限3到5人。 |
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上課時(shí)間和地點(diǎn) |
上課地點(diǎn)：【上�！浚和瑵�(jì)大學(xué)(滬西)/新城金郡商務(wù)樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學(xué)成教院 【北京分部】：北京中山/福鑫大樓 【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路） 【成都分部】：領(lǐng)館區(qū)1號（中和大道） 【沈陽分部】：沈陽理工大學(xué)/六宅臻品 【鄭州分部】：鄭州大學(xué)/錦華大廈 【石家莊分部】：河北科技大學(xué)/瑞景大廈 【廣州分部】：廣糧大廈 【西安分部】：協(xié)同大廈
近開課時(shí)間(周末班/連續(xù)班/晚班）： PrimeRail培訓(xùn)開班時(shí)間：2024年11月18日.....(請抓緊報(bào)名) |
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實(shí)驗(yàn)設(shè)備 |
☆資深工程師授課
☆注重質(zhì)量
☆邊講邊練
☆合格學(xué)員免費(fèi)推薦工作
專注高端培訓(xùn)17年，曙海提供的課程得到本行業(yè)的廣泛認(rèn)可，學(xué)員的能力
得到大家的認(rèn)同，受到用人單位的廣泛贊譽(yù)。
★實(shí)驗(yàn)設(shè)備請點(diǎn)擊這兒查看★ |
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新優(yōu)惠 |
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◆在讀學(xué)生憑學(xué)生證，可優(yōu)惠500元。 |
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質(zhì)量保障 |
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1、培訓(xùn)過程中，如有部分內(nèi)容理解不透或消化不好，可免費(fèi)在以后培訓(xùn)班中重聽；
2、培訓(xùn)結(jié)束后免費(fèi)提供半年的技術(shù)支持，充分保證培訓(xùn)后出效果；
3、培訓(xùn)合格學(xué)員可享受免費(fèi)推薦就業(yè)機(jī)會。 |
PrimeRail培訓(xùn) |
第一階段 |
Objectives
At the end of this workshop the student should be able to:
- Set up and perform Power/Ground (PG) reliability analysis for checking Static and Dynamic Voltage Drop and Electromigration (EM) potential violations
- Explanation of and/or set up the phases of Dynamic analysis of PrimeRail that involve the following:
- Library Characterization
- Data preparation
- Power Analysis
- PG Parasitic (RC) Extraction
- Dynamic (Transient) Rail Analysis
- Violation Viewing, Reporting and Correction
- What-if Analysis ? Package parasitics and Decap insertion
- Voltage Drop Derated Timing Analysis
- Accurate Hard Macro Modeling
- Power Management( power switch) Cell handling
- Set up PG analysis for hierarchical and top-level
- Use the PrimeRail graphical user interface (GUI) for the PG rail analysis, including what-if analysis
Audience Profile
????? Design, verification or CAD engineers who perform power/ground interconnect reliability analysis at the "Block" or "Full-Chip" levels. This covers a wide spectrum of designs of digital, memory, and analog/mixed signal.
Prerequisites
?????
Experience in the following areas is recommended to gain the most value from the workshop content:
- Physical layout
- Physical extraction
- Power simulation
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Static Analysis
- Introduction to Rail Analysis - requirements, capabilities and database preparation
- Power and Timing Model creation
- Power supply, net switching and Transition Time inputs
- Power and Rail Analysis
- Mapping, reporting, querying and what-if Analysis
- Integrated Flows - Hardmacro modeling, Power gating and Voltage derated timing analysis
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第二階段 |
Dynamic ( Transient) Analysis
- Introduction, database requirements and flows
- Library Characterization and LSF
- Cell-Level Dynamic Analysis-PP Run
- Cell-Level Dynamic Analysis-Transient Analysis
- What-if Analysis ? Package Parasitics and Decap Insertion
- Mapping, waveform viewing, reporting and querying
- Tx-Level Dynamic Analysis-Data Preparation
- Tx-Level Dynamic Analysis
- Tx-Level Signal EM Analysis
- Macro Modeling - Memory, Analog, custom or Hardmacro blocks
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